module reg_file_top(clk,rst,RegW,ra1,ra2,wa,wd,rd1,rd2);
  
  input clk,rst,RegW;
  input [4:0] ra1,ra2,wa;
  
  input [7:0] wd;
  
  output [7:0] rd1,rd2;
  
//  reg [7:0] wd;
  reg [7:0] rf[31:0];
//  reg Regwrite;
  
  
  always @(posedge clk)
  
    if (RegW) rf[wa] <= wd;
      
  assign rd1 = rf[ra1];
  assign rd2 = rf[ra2];
  
endmodule
